1. Field of the Invention
The present invention relates to a technique for transmitting/receiving data using a data bus.
2. Description of the Background Art
FIGS. 15 and 16 are diagrams each showing the structure of a conventional memory system constructed on a motherboard of a computer system. The diagrams show examples of a memory system that includes four DIMMs (Dual Inline Memory Modules) having DRAMs (Dynamic Random Access Memories). As shown in the diagrams, the four DIMMs (DIMM 0 to DIMM 3) and a memory controller 10 are connected through an address/command bus 11, a data bus 12, and clock lines 13.
Through the address/command bus 11 and the data bus 12, the memory controller 10 controls operations of the four DIMMs and also reads/writes data from/to the DIMMs. The address/command bus 11 transfers command signals (CMD) and address signals (ADD) from the memory controller 10 to the individual DIMMs. The command signals (CMD) are signals with which the memory controller 10 instructs the individual DIMMs to perform data writing or reading. The address signals (ADD) are signals for specifying addresses of the DRAMs to be read or written.
The data bus 12, which transfers data between the memory controller 10 and the individual DIMMs, is capable of transferring data in either direction between the memory controller 10 and the DIMMs. That is to way, when the memory controller 10 writes data into the DIMMs, the data bus 12 transfers data output (write data) from the memory controller 10 to the DIMMs; when the memory controller 10 reads data from the DIMMs, it transfers data output (read data) from the DIMMs to the memory controller 10.
Signals transferred through the data bus 12 between the memory controller 10 and the DIMMs include the data signal (DQ) to be written and read, data strobe signals (DQS) used when the memory controller 10 or the DRAMs in the DIMMs capture data, signals for masking data (DM), etc. Though not shown for the sake of simplicity, memory bus like the address/command bus 11 and the data bus 12 is each composed of a set of signal lines. For example, the data bus 12 carrying DQ/DQS/DM is generally composed of about 108 signal lines.
The memory controller 10 also sends a reference clock signal to the DIMMs through the clock lines 13: the reference clock signal has a reference frequency as an operating timing reference of the memory system.
The operation of the conventional memory system shown in FIG. 15 is now described briefly. For example, when writing data into a DIMM, the memory controller 10 first outputs a command signal (CMD) to the DIMM through the address/command bus 11 to indicate data writing and also outputs an address signal (ADD) to specify the write address. Then the memory controller 10 transfers the write data to the DIMM through the data bus 12 and the data is written in the specified address.
On the other hand, when reading data from the DIMM, the memory controller 10 first outputs a command signal (CMD) to the DIMM through the address/command bus 11 to indicate data reading and also outputs an address signal (ADD) to specify the read address. Then the data stored in the specified address in the DIMM is read out. The data (read data) is transferred through the data bus 12 to the memory controller 10 and read in by the memory controller 10.
When reflections occur during the transfer of a data signal on a memory bus like the address/command bus 11 or data bus 12, it causes signal distortion. Therefore, in order to suppress reflections, it is important to achieve impedance matching on the signal lines of the memory bus. Accordingly, each signal line of memory bus is generally terminated with a given terminating resistor.
For example, in FIG. 15, the data bus 12 is provided with series resistors Rs1 series-connected to the signal lines and terminating resistors Rt. The address/command bus 11 is provided with series resistors Rs2 series-connected to the signal lines. The terminating resistors Rt are connected to a given voltage Vtt which is usually set at a voltage about half the power-supply voltage. Though the individual signal lines forming the memory bus are not shown in the drawings, the signal lines of the memory bus have their respective series and terminating resistor.
In general, the signal distortion at the end receiving the transferred signal can be more effectively suppressed as the terminating resistor is placed closer to the receiving end. Since the data bus 12 transfers signals in both directions as mentioned earlier, terminating resistors may be connected as shown in FIG. 16 to the signal lines of the data bus 12, considering data transfer during data read from the DIMMs. That is to say, at a first end of the data bus 12 to which the memory controller 10 is connected, terminating resistors Rt2 may also be connected to the signal lines in a position closer to the memory controller 10 than the DIMMs (i.e between the memory controller 10 and the DIMMs). Then, during read operations from the DIMMs, distortions of signals received at the memory controller 10 can be suppressed more effectively than in the example of FIG. 15.
Recently, in order to increase the operating speed and to reduce the power consumption of memory systems, there is a tendency to set lower the amplitude of signals sent between the memory controller 10 and the DIMMs. This reduces the margin of signal amplitude, which increases the importance of suppressing the signal distortion. Therefore, in order to suppress signal distortion caused by reflections, it is becoming more important to achieve impedance matching by connecting series resistors and terminating resistors to the memory bus signal lines.
When signal lines bidirectionally transfer data, as the data bus 12 shown in the example above, and especially when the transferred signals have higher frequencies, it is difficult to well balance impedance matching during signal transfer in one direction and impedance matching during transfer in the other direction. That is to say, the signal distortion suppressing effect produced by the terminating resistors Rt1 and Rt2 and the series resistors Rs1 of the data bus 12 may differ in degree depending on the direction of data transfer. In this case, the series and terminating resistors provide unequal effects in suppressing the signal distortion during data write to the DIMMs (during data transfer from the memory controller 10 to the DIMMs) and during data read from the DIMMs (during data transfer from the DIMMs to the memory controller 10).
For example, when the impedance of each terminating resistor is set to effectively suppress signal distortion during data write to the DIMMs, then impedance mismatch occurs during read and distortion is caused in the waveform of the read data signal. This makes it necessary to allow some margin for the amplitude of signals transferred on the data bus 12, which hinders achievement of higher operating speed and reduced power consumption of the memory system.